The core of reducing distributed capacitance in planar transformers lies in reducing the electric field coupling area between windings, increasing insulation distance, and optimizing the layout design of the core and windings. Traditional transformers suffer from high interlayer capacitance due to their winding stacking method, while planar transformers use multi-layer PCBs or flexible printed circuits (FPCs) to replace copper wires, significantly reducing distributed capacitance through a flattened winding structure. Their optimization strategies can be developed from four dimensions: winding layout, core design, insulation material selection, and shielding layer application.
Winding layout is crucial for reducing distributed capacitance. Planar transformers typically employ interleaved winding or Z-shaped winding (folded winding) to reduce the voltage difference between adjacent layers by changing the winding arrangement. For example, Z-shaped winding alternates the starting ends of each winding layer, resulting in a more even distribution of the interlayer voltage difference and preventing capacitance concentration caused by localized high voltage differences. Furthermore, segmented winding divides the winding into multiple independent regions, further reducing the number of turns per layer and lowering interlayer capacitance. While these winding processes increase manufacturing complexity, they effectively suppress oscillations caused by leakage inductance and distributed capacitance during high-frequency switching, improving electromagnetic compatibility (EMC). The design of the magnetic core also significantly impacts distributed capacitance. Planar transformers often employ E-type, RM-type, or EER-type high-frequency power ferrite cores, whose geometry directly affects winding coupling efficiency and heat dissipation performance. For example, E-type cores offer large winding space, suitable for high-current applications, but require optimization of the core window width to reduce the number of winding layers. RM-type cores have a circular central post, which shortens the copper wire turn length, reducing copper losses and interlayer capacitance. Some designs utilize slots or integrated heat sinks on the core surface to create three-dimensional heat dissipation channels, reducing thermal resistance and minimizing insulation degradation caused by high temperatures, indirectly suppressing distributed capacitance growth.
The choice of insulation material is a direct means of controlling distributed capacitance. Planar transformers often use polyimide films or liquid metals (such as gallium-based alloys) as thermal interface materials (TIMs) for interlayer insulation, with significantly lower dielectric constants than traditional insulating paper. For example, the dielectric constant of polyimide film is only 3.5 at 1MHz, a 30% reduction compared to the 5.0 of traditional materials, effectively reducing dielectric losses. Furthermore, triple-insulated wires, through three insulation layers (polyamine film, spray-painted coating, and fiberglass layer), increase the withstand voltage between any two layers to AC 3000V, reducing distributed capacitance while increasing insulation distance, making them suitable for high-voltage applications.
The application of a shielding layer further isolates the electric field coupling between the primary and secondary windings. Faraday shielding layers, typically composed of copper foil or windings, are placed between the primary and secondary windings and grounded, reducing common-mode interference by shielding electric field lines. For example, in a 65W laptop adapter, a planar transformer using a "primary-shielding-secondary" sandwich structure reduces interlayer capacitance from 12pF to 3.2pF, lowering switching noise amplitude by 18dB. The shielding layer design must avoid short-circuit risks, typically using 0.9T or 1.1T thick copper foil to prevent short circuits in the magnetic field lines from causing the inductance to drop to zero.
Planar transformers achieve a significant reduction in distributed capacitance through optimized winding layout, improved core geometry, the application of low-dielectric-constant insulation materials, and integrated shielding layers. These structural optimizations not only improve energy conversion efficiency at high frequencies but also enhance electromagnetic compatibility and thermal stability, making them an ideal choice for high-frequency switching power supplies, inverters, and charging modules for new energy vehicles. With the widespread adoption of third-generation semiconductor devices, planar transformers are evolving towards higher frequencies (above 3MHz) and smaller sizes (EIA 1812 package). Their technological breakthroughs will continue to drive the power supply industry toward the goal of "zero volume and zero loss."
